Field of the Technology
The present invention relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array.
Description of Related Art
High density memory devices are being designed that comprise arrays of flash memory cells, or other types of memory cells. In some examples, the memory cells comprise thin film transistors which can be arranged in 3D architectures.
In one example, a 3D memory device includes a plurality of stacks of NAND strings of memory cells. The stacks include active strips separated by insulating material. The 3D memory device includes an array including a plurality of word lines structures, a plurality of string select structures, and ground select lines, arranged orthogonally over the plurality of stacks. Memory cells are formed at cross-points between the active strips in the plurality of stacks and the word lines structures.
One type of memory cells is referred to as a charge trapping memory cell, which uses a dielectric charge trapping layer. A typical charge trapping memory cell consists of a field effect transistor FET structure having a source and drain separated by a channel, and a gate separated from the channel by a charge storage structure including a tunnel dielectric layer, the dielectric charge trapping layer, and a blocking dielectric layer. According to the early conventional charge trapping memory designs referred to as SONOS (silicon-oxide-nitride-oxide-silicon) devices, the source, drain and channel are formed in a silicon body, the tunnel dielectric layer is formed of silicon oxide, the dielectric charge trapping layer is formed of silicon nitride, the blocking dielectric layer is formed of silicon oxide, and the gate includes polysilicon.
Another type of memory cells is referred to as a floating gate memory cell. A floating gate memory cell has a double gate MOSFET (metal-oxide-semiconductor field-effect transistor) structure including a control gate and a floating gate. A floating gate memory cell can be programmed to represent a logic level by trapping electrons on the floating gate and thus modifying the threshold voltage of the floating gate memory cell. The threshold voltage is the voltage applied to the control gate at which the double gate MOSFET becomes conductive.
The manufacturing process for a floating gate memory device can be more complicated than a charge trapping memory device, especially for three-dimensional arrays of floating gate memory cells. For instance, formation of floating gates in a floating gate memory device can require additional masks, such as when a SAMOS (Self-Aligned MOS) process is used as described in U.S. Pat. No. 7,153,780. Silicon nitride based charge-trapping device are relatively less complicated for process integration and manufacturing. Because silicon nitride is naturally an insulating film, there is no need to pattern silicon nitride with additional masks. In 3D NAND architectures, this could be an important advantage to minimize the processing integration complexity.
It is desirable to provide a floating gate structure for three-dimensional integrated circuit memory that reduces the complexity in manufacturing.